The present application generally relates to apparatuses such as television signal processing apparatus, that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must combine circuitry operating in a synchronous-sampling mode that must be adapted for use with a fixed rate sampling mode application.
Modern signal processing apparatus typically include signal processing circuitry for processing a multitude of signal formats, such as NTSC, ATSC, QAM, or satellite signals. Such a signal processing apparatus typically includes various components such as a tuner for selecting a particular signal or channel from a plurality of signals or channels received by the apparatus. To process digital signals, such as ATSC or satellite signals, the signal processing circuitry, and in particular the tuner, must perform these functions with high-speed digital circuitry. Some digital signal processing apparatus operate in a synchronous-sampling mode, where the A/D converter takes samples coincident with the digital symbol locations. The digital symbols, and subsequently the sampling frequency are calculated by the demodulator and a rate control signal is output from the demodulator to control the sampling rate of the A/D. It is also possible to take samples using an A/D converter at a fixed time intervals.
It is often a major design change in terms of time and expense to convert a design originally intended to operate in synchronous-sampling mode to operate in a fixed-rate sampling mode. This is primarily due to the requirement for an enable signal to be provided to all of the memory elements in the design. An enable signal is required throughout the design to identify when processing is to proceed since the demodulator is running at a high rate and not every clock signal is accompanied by a digital symbol. A thorough knowledge of the original design is usually required to effectuate the design change and re-verification is required to be carried out. In situations of design reuse, it would be advantageous to introduce a preprocessing block that can convert the fixed rate samples to synchronous samples with requiring the necessity of an enable line.
Furthermore, in digital signal processing applications, there are typically many different clocks used to drive the processing circuitry. These clocks are typically derived from a phase-locked loop (PLL). When the data is gathered through an A/D converter, using the PLL output to clock the A/D converter can degrade its performance as high speed A/D converters are sensitive to clock jitter. When an external clock is used to drive the A/D converter, a synchronization problem arises because of the unknown phase between the A/D clock and the PLL output clock. Previously, designers have used clock resynchronizers or back to back flip flops on the reference clock and PLL clock lines. This solution is based on the assumption that a “bad phase” occurs only some of the time. However, if the system starts up in the “bad phase” it will continue to operate constantly at the bad phase. This results in the data latching and putting the system into an unstable state. Therefore the robustness of the back-to-back flip flop approach is questionable. It is desirable to have an AND clock to be used by the digital signal processing circuitry that is synchronized to the PLL output clock to facilitate latching the AND output and preventing problems associated with clock jitter.